3.3. Integration of the photodetector
Integration of the photodetector into the same chip with the rest of the electronics entails several advantages. The stability of the receiver is improved, because the large parasitic capacitance and inductance between the photodetector and the input to the transimpedance preamplifier are reduced drastically. In addition, the bandwidth can be increased and the noise, size and mechanical complexity reduced. Production costs would also be lower, because the number of components decreases if the photodetector can be integrated into the same process without any process modifications.
The wavelength of the powerful semiconductor laser diodes used in pulsed TOF laser rangefinders (GaAs or AlGaAs) is 850...900 nm, so the optical signal can be detected using a silicon photodiode and will not limit implementation on the same chip as the rest of the receiver circuit. The size of the laser diode is ~100µm...300µm, and that of the photodetector should be of the same order if the optical parameters on the transmitter and receiver sides are equal.
The photodetector should be as sensitive as possible. An avalanche photodiode would give a higher response than conventional pin photodetectors because of internal gain. Integration of an APD is possible in standard processes and it gives a gain factor of up to thousand, but at the same time the excess noise factor rises to a level which prevents its use for pulsed TOF laser radar (Biber et al. 2001).
Several papers have been published in which photodiodes for wavelengths of 750ñ850nm have been integrated into silicon processes. These, together with the most important parameters, are summarised in Table 4.
Table 4. Comparison of Silicon Integrated Photodiodes at NIR wavelengths.
| R | η | λ | Process | BW / | VPD | Ref. |
|---|---|---|---|---|---|---|
| A/W | nm | µm | tr/tf | V | ||
| 0.541 | 0.821 | 850 | Mod.1.0 NMOS | 150 MHz | 32 | Schow et al. 1999 |
| 0.35 | 0.56 | 780 | Mod. CMOS | 7.24/11.8 ns | 3 | Zimmermann 1996 |
| 0.40 | 0.64 | 780 | Mod. CMOS | 1.26/1.27 ns | 3 | Zimmermann 1996 |
| 0.42 | 0.67 | 780 | Mod. CMOS | 0.63/0.7 ns | 3 | Zimmermann 1996 |
| 0.35 | 0.56 | 780 | Mod. Bipolar | 300 MHz | 3 | Yamamoto et al.1995 |
| 0.51 | 0.781 | 800 | Mod. Bipolar | 680 MHz | 10 | Kyomasu 1995 |
| 0.40 | 0.64 | 780 | Mod. BiCMOS | 0.26/0.22 ns | 20 | Zimmermann 1996 |
| 0.09 | 0.13 | 840 | SOI Bipolar | 1200 MHz | 5 | Ghioni et al. 1996 |
| 0.29 | 0.46 | 780 | 1.0 CMOS | 3.83/6.18 ns | 3 | Zimmermann 1996 |
| 0.04 | 0.06 | 850 | 0.35 CMOS | 1 Gb/s | 10 | Woodward et al.1998 |
| 0.28 | 0.41 | 850 | 0.8 CMOS | < 5 ns | 3.5 | Paper VII |
| 0.045 | 0.07 | 850 | 0.8 Bipolar | 3 Gb/s | Wieland et al. 1994 | |
| 0.07 | 0.10 | 850 | 0.6 BiCMOS | 700 MHz | 2.5 | Lim et al. 1993 |
| 0.31 | 0.45 | 850 | 1.2 BiCMOS | 30ns | 5.0 | Paper VII |
| 1) Anti-reflection coating | ||||||
The first eight lines of the table represents realisations in modified processes, whereas the last six lines show realisations without process modifications. Schow et al. (1999) reported on a lateral, interdigitated p-i-n photodiode fabricated directly on a high-resistivity n-type substrate. Zimmermann (1996) reported on several different photodiodes. That implemented in an unmodified 1.0µm CMOS twin-well process is a vertical n+/p-/p+ substrate photodiode. The three modified photodiodes are based on the same process but with changes in the thickness and concentration of the p- epitaxial layer. The best result has been achieved using a vertical p+/n-/n+ substrate photodiode in a modified 1.0µm CMOS twin-well process. Yamamoto et al. (1995) reported a vertical p+/n-/n-/n+-buried p-i-n photodiode in modified bipolar technology. The two n- layers are grown by high-resistive epitaxial layer formation. Kyomasu (1995) reported a vertical n+/p-/p+ photodiode in modified bipolar technology, where p- and n+ are epitaxial layers and the thickness of the high-resistivity p- layer is 30µm. Ghioni et al. (1996) reported on a lateral, interdigitated p-i-n photodiode on SOI, which is not usable in a standard manufacturing process.
Woodward et al. (1998) reported a p+/n-well photodiode implemented in a standard process in which interdigitated p- diffusion fingers inside the n-well form the active terminal. This enabled a higher speed to be obtained at the expense of responsivity, as the slow diffusion current tail originating from carriers diffusing from the p- substrate was screened away. Wieland et al. (1994) reported a photodiode using base and collector layers in bipolar technology. The detector was surrounded by a p+ substrate ring to help to collect the carriers generated below the base-collector junction and to keep crosstalk low, but this also reduced the quantum efficiency. Lim et al. (1993) reported a vertical p+/n-well/n+-buried layer p-i-n photodiode in which the thin (0.7 µm) “intrinsic” region could be depleted with a low bias voltage.
The photodiode implemented in 0.8µm CMOS technology presented in paper VII employs n+/n-well/p-/p+ substrate layers. The p- layer is epitaxially grown and is part of a standard n-well CMOS process. A cross-section of the photodiode is shown in Fig. 22.
The measured rise time of the photodiode was ~ 5 ns and the responsivity ~ 0.3 A/W. As the rise time of the preamplifier itself was about 4 ns, that of the photodiode must have been even less than 5 ns (paper VII).
A cross-section of the photodiode implemented in 1.2µm BiCMOS technology presented in paper VII, which uses n+/n-well/n+buried/p- substrate layers, is shown in Fig. 23.
The measured rise time of the photodiode was ~ 30 ns and the responsivity ~ 0.3 A/W. A pulse response consists of two parts: the fast rising edge of the output pulse caused by the drift current and a slow part caused by diffusion currents. Thus the effective responsivity is reduced in our application, where the length of the optical pulse (fwhm < 10 ns) is shorter than the rise time. The slow current tail in the response does not matter when the pulsing frequency is low compared with the lifetime of the minority carriers, i.e. all the minority carriers recombine before the next optical pulse arrives.
The main difference between the two processes described in paper VII from the point of view of the photodetectors is that the CMOS process has a highly doped p+ bulk below the epitaxially grown, lightly doped p- substrate while the p- substrate in the BiCMOS process is lightly doped throughout. This p+ bulk in the CMOS process reduces the effective lifetime of the diffusing electrons and thus suppresses the slow current tail and reduces the rise time without any significant reduction in responsivity. An additional advantage of the low-ohmic p+ bulk is the improved isolation between the detectors in a multi-detector circuit, because of the shortened effective diffusion length. Another difference between the processes lies in the existence of the n+ buried layer in the BiCMOS process, which slightly reduces the hole diffusion current and thus the responsivity, and also increases the capacitance as the depletion region is thinner.
Zhou et al. (1994) observed and investigated optoelectronic cross-talk with a NMOS transistor and resistor placed close to a pn photodiode which was illuminated with an 830 nm optical signal. They reported that a depleted diode guard ring reduced the crosstalk by ~85% about 30 µm away from the photodiode. This can be used to lower the cross-talk further in multi-detector circuits.
The responses of the photodiodes were simulated in a time-domain with a Matlab program that used continuity equations together with boundary conditions, process parameters and a step-type optical input signal. The measured rise times and responsivities agreed with the simulation results, and thus showed that the simulation works well (paper VII).
An ideal pn photodiode would have a depletion region width of about twice the penetration depth of light, and the layer would be located near the surface of the semiconductor (Sze 1981). In this way the depletion region would efficiently collect nearly all the electron-hole pairs generated and the capacitance of the junction would be small. The width of the depletion region should not be too large, however, as it should not increase the drift time across the junction too much. The responsivity of an ideal pn photodiode is 0.68 A/W at a wavelength of 850 nm, and the penetration depth of the photons is about 18 µm, which calls for a wide depletion region. The depth from the surface of the silicon from which all the minority carriers generated have to be collected in order to achieve a certain responsivity is shown in Fig. 24 as a function of wavelength. In order to achieve 0.5 A/W responsivity at a wavelength of 900 nm, the carriers have to be collected within 40 µm of the surface. The figure also shows that a wavelength of 650 nm would be better, but unfortunately no cheap, powerful pulsed semiconductor lasers are available at that wavelength.
Figure 24. Depths within which carriers have to be collected to achieve given responsivities as a function of wavelength.
The concentrations and depths of junctions cannot be freely adjusted in standard CMOS/BiCMOS processes, and the vertical dimensions are small compared with the penetration depth of the photons at NIR wavelengths. The results of the present work show, however, that a quantum efficiency of about 50% can be achieved even with a response time of a few nanoseconds. In addition, the lower noise partly compensates for the lower responsivity of the photodetector relative to realisations using external PIN photodiodes. The results indicate that photodetectors for a pulsed TOF laser radar module and imaging can be designed using standard CMOS/BiCMOS processes without any process modifications. This could lead to smaller, cheaper and simpler realisations in some applications.